TECHNIQUES FOR PREFETCHING DATA TO A FIRST LEVEL OF MEMORY OF A HIERARCHICAL ARRANGEMENT OF MEMORY
The invention relates to techniques for prefetching data to a first level of memory of a hierarchical arrangement of a memory. Examples include techniques to prefetch data from a second level of memory of a hierarchical arrangement of memory to a second level of memory of the hierarchical arrangemen...
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Main Authors | , |
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Format | Patent |
Language | Chinese English |
Published |
11.10.2019
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Subjects | |
Online Access | Get full text |
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Summary: | The invention relates to techniques for prefetching data to a first level of memory of a hierarchical arrangement of a memory. Examples include techniques to prefetch data from a second level of memory of a hierarchical arrangement of memory to a second level of memory of the hierarchical arrangement of memory. Examples include circuitry for a processor receiving a prefetch request from a core ofthe processor to prefetch data from the first level to the second level. The prefetch request indicating an amount of data to prefetch that is greater than a data capacity of a cache line utilized bythe core.
本发明涉及用于将数据预取到分级存储器布置的第一级存储器的技术。示例包括用于将数据从分级存储器布置的第二级存储器预取到分级存储器布置的第一级存储器的技术。示例包括用于处理器的电路接收来自处理器的核的要将数据从第二级存储器预取到第一级存储器的预取请求。预取请求指示大于核所利用的高速缓存行的数据容量的要预取的数据量。 |
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Bibliography: | Application Number: CN201910151669 |