Chip design method to optimize circuit performance according to PVT operation condition change

• Main Authors: KIM JI YOUN, HWANG EUN JU
• Format: Patent
• Language: Chinese; English
• Published: 16.08.2019
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A method of designing a chip having an integrated circuit is provided. The method includes obtaining delta cell delays and delta net delays according to a process, voltage, and temperature (PVT) corner change with respect to a plurality of cells and a plurality of nets forming the integrated circuit; analyzing sensitivity with respect to a delay according to the PVT corner change of a plurality ofpaths in the integrated circuit, by using the delta cell delays and the delta net delays; determining N-number of sensitivity-critical paths among the plurality of paths based on a result of the analysis, wherein N is an integer greater than or equal to 0; and performing an engineering change order (ECO) based on a result of the determination. 提供了一种设计具有集成电路的芯片的方法。该方法包括：获得关于形成集成电路的多个单元和多个连线的根据工艺、电压和温度(PVT)端角变化的增量单元延迟和增量连线延迟；通过使用增量单元延迟和增量连线延迟，分析关于根据集成电路中的多个路径的PVT端角变化的延迟的灵敏度；基于分析的结果确定所述多个路径当中的N个灵敏度关键路径，其中N是大于或等于0的整数；以及基于确定的结果执行工程变更命令(ECO)。