LOGIC CIRCUIT BLOCK LAYOUTS WITH DUAL-SIDED PROCESSING

• Main Authors: RICHAUD JEAN, GOKTEPELI SINAN
• Format: Patent
• Language: Chinese; English
• Published: 02.08.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An integrated circuit device may include a p-type metal oxide semiconductor (PMOS) transistor supported by a backside of an isolation layer (620). The integrated circuit device may also include an n-type metal oxide semiconductor (NMOS) transistor supported by a front-side of the isolation layer, opposite the backside. The integrated circuit device may further include a shared contact (640) extending through the isolation layer and electrically coupling a first terminal of the PMOS transistor to the first terminal of the NMOS transistor. 一种集成电路器件可以包括由隔离层(620)的背面支撑的p型金属氧化物半导体(PMOS)晶体管。集成电路器件还可以包括由隔离层的与背面相对的正面支撑的n型金属氧化物半导体(NMOS)晶体管。集成电路器件可以进一步包括共享接触部(640)，其延伸穿过隔离层，并且将PMOS晶体管的第一端子电耦合到NMOS晶体管的第一端子。