Digital integrated circuit layout method based on discrete optimization and terminal device

The invention discloses a digital integrated circuit layout method based on discrete optimization and a terminal device, and the method comprises the steps: randomly generating a preset number of first layouts of standard unit position discrete codes in advance, and adjusting the first layouts to ob...

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Bibliographic Details
Main Author ZENG QIMING
Format Patent
LanguageChinese
English
Published 02.08.2019
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The invention discloses a digital integrated circuit layout method based on discrete optimization and a terminal device, and the method comprises the steps: randomly generating a preset number of first layouts of standard unit position discrete codes in advance, and adjusting the first layouts to obtain second layouts without layout conflicts; obtaining a first total connection line length of eachsecond layout, and optimizing each second layout by adopting a discrete evolution algorithm to obtain each third layout; carrying out local optimization on the third layout by adopting a greedy algorithm to obtain fourth layouts, and respectively calculating second total connection line lengths of the fourth layouts; and selecting an optimal layout from all the fourth layouts according to the length of the second total connection line, and arranging the standard cell on the substrate according to the optimal layout. According to the method, the standard cell positions are discretely coded, and the layout is optimized
Bibliography:Application Number: CN201910381133