WORDLINE BRIDGE IN A 3D MEMORY ARRAY

• Main Authors: THIMMEGOWDA DEEPAK, MEYAARD DAVID S, HASNAT KHALED, JUNGROTH OWEN W
• Format: Patent
• Language: Chinese; English
• Published: 07.06.2019
• Subjects: ELECTRICITY; INFORMATION STORAGE; PHYSICS; STATIC STORES

The present disclosure relates to providing a wordline bridge between wordlines of adjacent tiles of memory cells to reduce the number wordline staircases in 3D memory arrays. An apparatus may includea memory array having memory cells. The memory array includes a first block of pages of the memory cells in a first tile and a second block of pages of the memory cells in a second tile. The apparatus may also include a polysilicon wordline bridge that couples first wordlines of the first block to second wordlines of the second block to couple the first tile to the second tile. The wordline bridge may be formed by applying a hard mask over the first tile, the second tile, and over a portion of polysilicon that connects the first tile to the second tile. 本发明公开了3D存储器阵列中的字线桥。本公开内容涉及在存储器单元的相邻瓦片的字线之间提供字线桥，用以减小3D存储器阵列中的字线阶梯的数目。一种装置可以包括具有存储器单元的存储器阵列。所述存储器阵列包括第一瓦片中的存储器单元的页面的第一块以及第二瓦片中的存储器单元的页面的第二块。所述装置还可以包括多晶硅字线桥，所述多晶硅字线桥将所述第一块的第一字线耦合到所述第二块的第二字线，用于将所述第一瓦片耦合到所述第二瓦片。所述字线桥可以通过如下来被形成：在所述第一瓦片、所述第二瓦片上方以及在将所述第一瓦片连接到所述第二瓦片的多晶硅的一