Method and apparatus for clock phase generation

• Main Authors: HEARNE CATHERINE, UPADHYAYA PARAG, MANTHENA VAMSHI, ERETT MARC, RAJ MAYANK, NAMKOONG JINYUNG
• Format: Patent
• Language: Chinese; English
• Published: 15.03.2019
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit (100) includes an injection locked oscillator (102), a loop controller (116), and aphase interpolator (108). The injection locked oscillator (102) includes an input for receiving an injected clock signal (112) and an output for forwarding a set of fixed clock phases. The loop controller (116) includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltagematches the free running frequency of the injection locked oscillator (102) to a frequency of the injected clock signal (112). The phase interpolator (108) includes an input for receiving the set offixed clock phases directly from the injection locked oscillator (102), an input for receiving the supply voltage from the loop controller (116), and an output for forwarding an arbitrary clock phase. 本申请公开了种用于时钟相位生成的方法、非暂时性计算机