Electronic packaging structure, packaging substrate and preparation method thereof

The invention provides an electronic packaging structure, a packaging substrate and a preparation method thereof. The invention provides the packaging substrate which comprises an insulating part, a line part which is combined with the insulating part, and a supporting member arranged on the insulat...

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Main Authors MI HSUAN HAO, CHEN CHIA CHENG, WU QIRUI, LIN CHUN HSIEN, PAI YU CHENG
Format Patent
LanguageChinese
English
Published 05.03.2019
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Abstract The invention provides an electronic packaging structure, a packaging substrate and a preparation method thereof. The invention provides the packaging substrate which comprises an insulating part, a line part which is combined with the insulating part, and a supporting member arranged on the insulating part. Furthermore the supporting member has an opening which exposes part of the line part so that a testing device can perform electric testing on the line part before executing a crystal packaging process, thereby determining whether the electric property of the packaging substrate is defective and preventing arranging a good wafer on a defective packaging substrate. 种电子封装结构及其封装基板与制法,其提供包含有绝缘部、结合于该绝缘部的线路部及设于该绝缘部上的支撑件的封装基板,且该支撑件具有外露部分该线路部的开口,使检测装置能于进行置晶封装制程前针对该线路部进行电测,以得知该封装基板的电性是否不良,避免将良好的晶片设于不良的封装基板上。
AbstractList The invention provides an electronic packaging structure, a packaging substrate and a preparation method thereof. The invention provides the packaging substrate which comprises an insulating part, a line part which is combined with the insulating part, and a supporting member arranged on the insulating part. Furthermore the supporting member has an opening which exposes part of the line part so that a testing device can perform electric testing on the line part before executing a crystal packaging process, thereby determining whether the electric property of the packaging substrate is defective and preventing arranging a good wafer on a defective packaging substrate. 种电子封装结构及其封装基板与制法,其提供包含有绝缘部、结合于该绝缘部的线路部及设于该绝缘部上的支撑件的封装基板,且该支撑件具有外露部分该线路部的开口,使检测装置能于进行置晶封装制程前针对该线路部进行电测,以得知该封装基板的电性是否不良,避免将良好的晶片设于不良的封装基板上。
Author LIN CHUN HSIEN
MI HSUAN HAO
WU QIRUI
PAI YU CHENG
CHEN CHIA CHENG
Author_xml – fullname: MI HSUAN HAO
– fullname: CHEN CHIA CHENG
– fullname: WU QIRUI
– fullname: LIN CHUN HSIEN
– fullname: PAI YU CHENG
BookMark eNrjYmDJy89L5WQIcs1JTS4pys_LTFYoSEzOTkzPzEtXKC4pKk0uKS1K1UEWLE0CiieWpCok5qUoFBSlFiQCeZn5eQq5qSUZ-SkKJRmpRan5aTwMrGmJOcWpvFCam0HRzTXE2UM3tSA_PrUYaGBqXmpJvLOfoYGliZG5uZGZozExagCq8zqV
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
DocumentTitleAlternate 电子封装结构及其封装基板与制法
ExternalDocumentID CN109427726A
GroupedDBID EVB
ID FETCH-epo_espacenet_CN109427726A3
IEDL.DBID EVB
IngestDate Fri Jul 19 16:13:29 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language Chinese
English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_CN109427726A3
Notes Application Number: CN20171826338
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190305&DB=EPODOC&CC=CN&NR=109427726A
ParticipantIDs epo_espacenet_CN109427726A
PublicationCentury 2000
PublicationDate 20190305
PublicationDateYYYYMMDD 2019-03-05
PublicationDate_xml – month: 03
  year: 2019
  text: 20190305
  day: 05
PublicationDecade 2010
PublicationYear 2019
RelatedCompanies SILICONWARE PRECISION INDUSTRIES CO., LTD
RelatedCompanies_xml – name: SILICONWARE PRECISION INDUSTRIES CO., LTD
Score 3.3168366
Snippet The invention provides an electronic packaging structure, a packaging substrate and a preparation method thereof. The invention provides the packaging...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title Electronic packaging structure, packaging substrate and preparation method thereof
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190305&DB=EPODOC&locale=&CC=CN&NR=109427726A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mFPVNp6LzgwjSJ4uzX2sfhri0Ywjrxpiyt5G0CVOhLdtE8K_3knUfL_oWEjjujlzul6_fAdz5TLqp3WyYzOe26fjMNoOGTE0mAt5IUuH5-va8F3vdV-dl7I4r8LH6C6N5Qr81OSJGVILxvtDrdbE5xAr128r5A3_HrvypM2qFRrk7xuyG89cI261o0A_71KC0RWMjHiLWDRwLkaT3vAO7CkYrnv3ora1-pRTbKaVzBHsDlJYtjqHyM63BAV1VXqvBfq-88MZmGXvzExhG64o1BHX-1OWFyJL_9Wsm7rc7cTXQrLOEZSkpZmJJ8J1nZFkwmijUJ3J5CredaES7Jio3WXtiQuONHfYZVLM8E-dAxKPDfcmbliJH467F_CDxbEdKRyE-llxA_W859f8GL-FQeVU_unKvoIo2iWvMwgt-o933CzZejeg
link.rule.ids 230,309,786,891,25594,76904
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mFOebTkXnVwTpk8Vu_Vj7MMSlHVPXbowqextJm-IHtGObCP71XrPu40XfwgWO5Mh9JJf7HcCNzRIz1puaymyuq4bNdNXRklhlwuFaFAvLltlzP7C6L8bTyByV4GNZCyNxQr8lOCJqVIT6Ppf2erJ-xHLl38rZHX9HUnbfCVuuUtyO0bvh-VXcdssb9N0-VSht0UAJhhjrOkYDI0nrYQu2m3glzHH2vdd2XpUy2XQpnX3YGSC3dH4ApZ-3KlTosvNaFXb9IuGNw0L3Zocw9FYdawiu-VO2FyIL_NevqbjdJKI1kKizhKUxmUzFAuA7S8miYTTJoz6RJUdw3fFC2lVxceOVJMY0WO9DP4ZymqXiBIioG9xOeLORg6Nxs8FsJ7J0I0mMPOJj0SnU_uZT-2_yCird0O-Ne4_B8xns5RKWH7DMcyjj_sQFeuQ5v5Si_AX_lpDT
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Electronic+packaging+structure%2C+packaging+substrate+and+preparation+method+thereof&rft.inventor=MI+HSUAN+HAO&rft.inventor=CHEN+CHIA+CHENG&rft.inventor=WU+QIRUI&rft.inventor=LIN+CHUN+HSIEN&rft.inventor=PAI+YU+CHENG&rft.date=2019-03-05&rft.externalDBID=A&rft.externalDocID=CN109427726A