CHIP PACKAGE INTERACTION (CPI) BACK-END-OF-LINE (BEOL) MONITORING STRUCTURE AND METHOD

• Main Authors: POZDER SCOTT K, CHUA ENG CHYE
• Format: Patent
• Language: Chinese; English
• Published: 01.02.2019
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Various embodiments include monitoring structures for integrated circuits (ICs) and related monitoring methods. In some cases, a monitoring structure includes: a set of serpentine-comb structures configured to connect with a back-end-of-line (BEOL) portion of the IC, each of the serpentine-comb structures including: a chain of interconnected laterally extending wires spanning a set of metal levelsin the IC; and a set of vias connecting the chain of interconnected laterally extending wires across the set of metal levels, wherein the set of vias includes at least one via spanning between each successive level of the chain of interconnected laterally extending wires, wherein the chain of interconnected laterally extending wires and the set of vias are configured to detect a chip package interface (CPI) failure in the IC. 本发明涉及芯片封装交互后段工艺监测结构及方法，各种实施例包括集成电路(IC)的监测结构及其相关监测方法。在某些情况下，监测结构包括：组蛇形梳齿结构，其被配置为连接该IC的后端工艺(BEOL)部分，各该蛇形梳齿结构包括：链互连的横向延伸的导线，其贯穿该IC的组金属层；以及组通孔，其连接贯穿该组金属层的该链互连的横向延伸的导线，其中，该组通孔包括于该链互连的横向延伸的导线的各连续层之间贯穿