Memory-network processor with programmable optimizations

• Main Authors: GIBSON DAVID A, BEARDSLEE JOHN MARK, DOBBS CARL S, TROCINO MICHAEL R, BINDLOSS KEITH M, ARYA SUMEER, SOLKA MICHAEL B, DOERR MICHAEL B, FAULKNER KENNETH R
• Format: Patent
• Language: Chinese; English
• Published: 29.01.2019
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths. 本发明涉及具有可编程优化的存储器-网络处理器。公开了具有为高性能和低功耗而优化的处理元件的多处理器系统以及编程处理元件的关联方法的各种实施例。每