METHOD OF CONTROLLING WAFER BOW IN TYPE III-V SEMICONDUCTOR DEVICE

• Main Authors: TUNGARE MIHIR, WAN JIANWEI, PARK SEONG-EUN, KIM PETER-WOOK, KANNAN SRINIVASAN
• Format: Patent
• Language: Chinese; English
• Published: 28.12.2018
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. The type III-V semiconductor lattice transition region includes at least a first Group III element, a second Group III element and at least one Group V element. The type III-V semiconductor lattice transition region includes a first lattice transition layer formed over the type IV semiconductor substrate, the first lattice transition layer having a firstconcentration of the first Group III element, a second lattice transition layer formed over the first lattice transition layer, the second lattice transition layer having a second concentration of thefirst Group III element t