Failure analysis positioning method
The invention discloses a failure analysis positioning method, and belongs to the technical field of semiconductors. The failure analysis positioning method comprises the following steps: steps S1, arranging a target area in a repetitive structural region in advance; step S2, arranging a dot-matrix...
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Main Authors | , , , |
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Format | Patent |
Language | Chinese English |
Published |
30.11.2018
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Subjects | |
Online Access | Get full text |
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Summary: | The invention discloses a failure analysis positioning method, and belongs to the technical field of semiconductors. The failure analysis positioning method comprises the following steps: steps S1, arranging a target area in a repetitive structural region in advance; step S2, arranging a dot-matrix graphic on the surface of a tested chip by taking the target area as a center, the area of composition dots in the dot-matrix graphic is in positive correlation with the distance between the composition dots and the target area; step S3, performing failure analysis on the target area to position failure dots in the target area, positioning the target area according to the dot-matrix graphic before performing the failure analysis. The beneficial effect of the failure analysis positioning method is that the time of grasping the failure dots can be reduced, so that the failure analysis can be performed quickly, the efficiency of the failure analysis is improved, and the fast positioning and analysis of the failure dot |
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Bibliography: | Application Number: CN20181619924 |