Reconfigurable chip architecture for high-traffic network processing

• Main Authors: ZHAO PEI, TAO SHUTING, YAN PAN, MAO YAXIN, NIU JIANZE
• Format: Patent
• Language: Chinese; English
• Published: 13.11.2018
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; MULTIPLEX COMMUNICATION; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

The invention discloses a reconfigurable chip architecture for high-traffic network processing. The reconfigurable chip architecture comprises an ingress policy module, a network message header processor and an egress policy module, wherein the ingress policy module slices a message, stores the message slices containing the payload of message data, and adds a corresponding storage address to the message header slices, and then assigns a sequence number to the message header slices, and assigns the message header slices carrying sequence number information to micro-engines with more idle threads; the network message header processor adopts multiple independent micro-engines to parse, classify and forward the received message header slices in parallel; the egress policy module parses a message header, extracts the payload of the message data from the cache, and splices the payload of the message data with the corresponding message header to form a complete message; and all messages are sequentially subjected to