Integrated circuit with improved resistive region

• Main Authors: STEPHAN NIEL, BENOIT FROMENT, ARNAUD REGNIER, ABDERREZAK MARZAKI
• Format: Patent
• Language: Chinese; English
• Published: 07.09.2018
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The application relates to an integrated circuit with an improved resistive region. An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An uppertrench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region. 本申请涉及具有改进的电阻区域的集成电路。集成电路包括具有电隔离的半导体阱的半导体衬底。上部沟槽隔离件从半导体阱的正面延伸到距离阱的底部定距离的深度。两个附加隔离区域与半导体阱电绝缘，并且沿第方向在半导体阱的内部延伸，并且从半导体阱的正面垂直延伸到半导体阱的底部。至少个经包围的电阻区域由两个附加隔离区、上部沟槽隔离件和半导体阱的底部来界定。电接触件被电耦合到经包围的电阻区域。