Single event hardening-based programmable double-data-rate register circuit and control method

• Main Authors: WANG WENFENG, CHEN LEI, NI JIE, LI QI, GUO KUN, SUN HUABO, SUN JIANSHUANG, LIU YAZE, QIAN TAOTAO
• Format: Patent
• Language: Chinese; English
• Published: 27.07.2018
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

The invention discloses a single event hardening-based programmable double-data-rate register circuit and a control method. A circuit with a dual-redundancy interlocking structure is adopted for a conventional latch to realize single event hardening design of a register storage unit; and based on this, a clock generation circuit, a data multiplexer and a data retaining circuit are added for controlling a time sequence of multiple registers with dual-redundancy interlocking structures, so that multi-mode double-data-rate register functions can be realized. A single event hardening index is improved by three orders of magnitude in comparison with that of a conventional register, and programmable functions of a level latch, a single-data-rate edge trigger, a reverse-edge-mode double-data-rateedge trigger, a same-edge-mode double-data-rate edge trigger and the like can be realized, so that higher flexibility, better time sequence performance and extremely high anti-single event hardeningindex are achieved during