MULTI-CORE COMMUNICATION ACCELERATION USING HARDWARE QUEUE DEVICE

• Main Authors: TSAI JR-SHIAN, VAN DOREN STEPHEN R, VANGATI NARENDER, MCDONNELL NIALL D, HERDRICH ANDREW J, VERPLANKE EDWIN, CLEE JAMES T, WHITESELL JAMISON D, KENNY JONATHAN, WANG REN, SONNIER DAVID, HASTING JOSEPH R, PIROG JERRY, TAI TSUNG-YUAN C, WILKINSON HUGH, MA TE K, BURROUGHS WILLIAM, EADS GAGE, WANG YIPENG, BURRES BRADLEY A, YAN AN, VENKATESAN NAMAKKAL N, RICHARDSON BRUCE, BERNSTEIN DEBRA, CUNNINGHAM ANDREW, MILLER STEPHEN
• Format: Patent
• Language: Chinese; English
• Published: 17.07.2018
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

Disclosed are apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus includes multi-core processors, a shared L3 or last-level cache (''LLC''), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate, in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device. 实现硬件队列管理设备的装置和方法，该硬件队列管理设备用于通过从CPU核心卸载请求管理和数据致性任务来减少核心间的数据传输开销。所述装置包括多核心处理器、共享的L3或末级高速缓存（"LLC"）、以及硬件队列管理设备用以接收、存储和处理核心间的数据传输请求。硬件队列管理设备进步包括资源管理系统用以控制核心可以提交请求以减少核心停机和丢弃的请求的速率。此外，引入软件指令来优化核心与队列管理设备之间的通信。