N-way monitor

• Main Authors: WIM HEIRMAN, YVES VANDRIESSCHE
• Format: Patent
• Language: Chinese; English
• Published: 06.07.2018
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses an N-way monitor. A processor core includes a decode circuit to decode an instruction, where the instruction specifies an address to be monitored. The processor core further includes a monitor circuit, where the monitor circuit includes a data structure to store a plurality of entries for addresses that are being monitored by the monitor circuit and a triggered queue, wherethe monitor circuit is to enqueue an address being monitored by the monitor circuit into the triggered queue in response to a determination that a triggering event for the address being monitored bythe monitor circuit occurred. The processor core further includes an execution circuit to execute the decoded instruction to add an entry for the specified address to be monitored into the data structure and ensure, using a cache coherence protocol, that a coherency status of a cache line corresponding to the specified address to be monitored is in a shared state. 本申请公开了N路监测器。处理器核包括解码电路，该解码电路用于对指令解码，其中所述指令指定要监测的地址；处理器核进步包括