Terminal and slow clock frequency offset adjustment method thereof

• Main Author: LU YUPENG
• Format: Patent
• Language: Chinese; English
• Published: 26.06.2018
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; MULTIPLEX COMMUNICATION

The present invention provides a terminal and a slow clock frequency offset adjustment method thereof. The terminal comprises a digitally compensated crystal oscillator (DCXO) for generating a reference clock. A relationship between CDAC and the output frequency of the DCXO is determined; a corresponding output frequency of the DCXO under a condition that the CDAC is minimum is obtained, and the first load capacitance of the DCXO at this moment is obtained; and the CDAC is the coarse adjustment capacitance of the working circuit of the DCXO. A relationship between CFAC and the output frequencyof the DCXO is determined; a corresponding output frequency of the DCXO under a condition that the CFAC is minimum is obtained; the second load capacitance of the DCXO at this moment is obtained; andthe CFAC is the fine adjustment capacitance of the working circuit of the DCXO. The minimum load capacitance of the DCXO is obtained according to the first load capacitance and the second load capacitance. A first frequency o