Software simulation verification system of programmable logic device on basis of system model

• Main Authors: WANG YING, ZHENG JINYAN, LIU WEI, ZHANG CONG, GAO XIAOQIONG, MENG QI, LI ZHIGANG, CHEN PAN, MA PEIPEI, LI CHUNJING, WEI WEIBO, LI ANG, SUN WENJING, AN PENGWEI, KANG JIANTAO, ZHANG QING, CHEN PENG, WANG YINGCHAO, ZHANG YIYI, JI WEIWEI
• Format: Patent
• Language: Chinese; English
• Published: 05.06.2018
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention belongs to the technical field of FPGA software simulation testing, and particularly relates to a software simulation verification system of a programmable logic device on the basis of asystem model. Compared with the prior art, according to the technical scheme, the problem is solved that a tester needs to edit codes line by line to simulate an FPGA peripheral interface component in existing FPGA simulation tests. The system is independently developed, verified FPGA peripheral interface functions are encapsulated in the bottom layer, an upper layer model conducts callling and parameterized configuration on the functions, and the problem is solved that manual simulation of the FPGA peripheral interface component affects the efficiency and the correctness and accuracy of theinterface component. 本发明属于FPGA软件仿真测试技术领域，具体涉及种基于系统模型的可编程逻辑器件软件仿真验证系统。与现有技术相比较，本发明通过实施上述技术方案，较好的解决了现有FPGA仿真测试中，需要测试人员逐行编辑代码模拟FPGA外围接口器件的问题。本系统自主研发并经过验证的FPGA外围接口函数封装在底层，上层模型对其进行调用和参数化配置，解决了需要人工模拟FPGA外围接口器件所带来的影响效率的问题和接口器件正确性和准确性