NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE

• Main Authors: PANDITA BUPESH, COHEN HANAN, ARCUDIA KENNETH LUIS, HAILU ESKINDER
• Format: Patent
• Language: Chinese; English
• Published: 17.04.2018
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages,inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage. 在个实施例中，种用于频率划分的方法包括：将模信号从级联的划分器级中的最后划分器级向划分器级中的第划分器级沿划分器级的链向上传播，并且针对划分器级中的每个划分器级，当模信号传播出划分器级时生成相应的本地负载信号。该方法还包括：针对划分器级中的每个划分器级，基于相应的本地负载信号向划分器级输入个或多个相应的控制位，个或多个相应的控制位设置划分器级的划分器值。