Wafer level packaging using lead-frame

• Main Author: ASHRAFZADEH AHMAD R
• Format: Patent
• Language: Chinese; English
• Published: 09.02.2018
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Disclosed is wafer level packaging using a lead-frame. When used to package two or more chips, a final product will have QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed. 种使用引线框架的晶圆级封装件。当用于封装两个或多个芯片时，最终产品具有类似于方形扁平无引脚封装(QFN)的处理后表面。最终产品也将具有匹敌或超过相应的单片芯片的性能，因为两个或多个芯片能够紧密连接并且能够将每个芯片的制造处理过程定制为仅适应所述芯片上的器件的要求。晶圆级封装还可以用于封装单片芯片，也可以用于封装在个芯片具有源器件且在第二芯片上具有无源器件的多个芯片。公开了多种示例性实施例。