IMPEDANCE CALIBRATION CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

• Main Authors: SEOK-JIN CHO, TAE-YOUNG OH
• Format: Patent
• Language: Chinese; English
• Published: 24.11.2017
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

An impedance calibration circuit includes a first code generator, a first code storing circuit, a second code generator and a second code storing circuit. The first code generator generates a pull-up control code obtained from a result of comparing a target output high level (VOH) voltage with a first voltage of a first node. The first code storing circuit stores the pull-up control code when the target VOH voltage becomes the same as the first voltage. The second code generator generates a pull-down control code obtained from a result of comparing the VOH voltage with a second voltage of a second node. The second storing circuit stores the pull-down control code when the target VOH voltage becomes the same as the second voltage. The first code storing circuit and the second code storing circuit store pull-up control code and pull-down control code pairs respectively. 种阻抗校准电路，包括第代码生成器、第代码存储电路、第二代码生成器和第二代码存储电路。所述第代码生成器生成上拉控制码，该上拉控制码是从比较目标输出高电平(VOH)电压与第结点的第电压所得的结果而获得的。当所述目标VOH电压变成与所述第电压相同时，所述第代码存储器电路存储所述上拉控制码。所