Layout checking system and method

The embodiment of the invention provides a layout checking method that includes the operation below. Groups, indicating layout patterns of interconnection layers, are assigned to a circuit, to determine layout constraints of the circuit. Layout patterns are extracted from a layout design for the cir...

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Bibliographic Details
Main Authors HSIEH YAO-JEN, LIU KAI-MING
Format Patent
LanguageChinese
English
Published 29.08.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The embodiment of the invention provides a layout checking method that includes the operation below. Groups, indicating layout patterns of interconnection layers, are assigned to a circuit, to determine layout constraints of the circuit. Layout patterns are extracted from a layout design for the circuit. The layout patterns are compared with the layout constraints. Data, indicating the layout design, for fabrication of the circuit are generated in a condition that the layout patterns meet the layout constraints. The embodiment of the invention further provides a layout checking system. 本发明的实施例提供种布局检查方法，包括以下操作。将指示互连层的布局图案的组分配给电路，以确定电路的布局约束。从用于电路的布局设计中提取布局图案。将布局图案与布局约束比较。在布局图案满足布局约束的情况下生成用于电路的制造的指示布局设计的数据。本发明的实施例还提供了种布局检查系统。
Bibliography:Application Number: CN201710023963