MEMORY DEVICE

• Main Authors: PARK JIN TAEK, LEE SUNG YUN, YOU JANG HYUN, SHIN TAEK SOO
• Format: Patent
• Language: Chinese; English
• Published: 04.08.2017
• Subjects: ELECTRICITY

The invention relates to a memory device. The memory device comprises a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches. 本公开涉及存储器件。种存储器件，其包括衬底、多个沟道柱、栅堆叠、层间绝缘层、多个第沟槽、以及至少个第二沟槽。衬底包括单元阵列区和连接区。沟道柱在单元阵列区中与衬底的上表面交叉。栅堆叠包括围绕单元阵列区中的构道柱的多个栅电极层。栅电极层在连接区中延伸至不