High-k-last manufacturing process for embedded memory with metal-oxide-nitride-oxide-silicon (MONOS) memory cells

• Main Authors: WEI CHENG WU, IING CHEN
• Format: Patent
• Language: Chinese; English
• Published: 07.07.2017
• Subjects: ELECTRICITY

An integrated circuit (IC) using high-K metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high K dielectric layers. A high-K-last method for manufacturing the IC is also provided. 本发明提供了些使用高介电层金属栅极(HKMG)技术的具有嵌入式金属-氧化物-氮化物-氧化物-硅(MONOS)存储单元的集成电路(IC)。逻辑器件布置在半导体衬底上，并且包括逻辑栅极。存储单元布置在半导体衬底上，并且包括彼此横向邻近的控制晶体管和选择晶体管。控制晶体管和选择晶体管分别包括控制栅极和选择栅极，以及控制晶体管还包括位于控制栅极下方的电荷捕获层。逻辑栅极以及控制栅极和选择栅极的个或两个是金属，以及布置在相应的高介电层中。本发明也提供了制造高介电层IC的高介电层后制方法。本发明实施例涉及种集成电