Batch testing method and batch testing system for chips
The invention discloses a batch testing method and a batch testing system for chips. The method comprises the steps of S300, transmitting testing instruction information to a first bus port of a to-be-tested chip through a data signal bus; S400, receiving the testing instruction information which is...
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Main Authors | , , , , |
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Format | Patent |
Language | Chinese English |
Published |
10.05.2017
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Subjects | |
Online Access | Get full text |
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Summary: | The invention discloses a batch testing method and a batch testing system for chips. The method comprises the steps of S300, transmitting testing instruction information to a first bus port of a to-be-tested chip through a data signal bus; S400, receiving the testing instruction information which is transmitted from a master control chip by the to-be-tested chip through the first bus port; S500, transmitting a response instruction to the master control chip by the to-be-tested chip according to first preset address information; S600, determining the operation state of the to-be-tested chip by the master control chip according to the response instruction of the first preset address information, and when the operation state is abnormal, executing a step S700; and S700, replacing the abnormal to-be-tested chip by means of the to-be-tested chip in the first preset address information. The batch testing method and the batch testing system realize simultaneous testing on a large batch of chips and furthermore can m |
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Bibliography: | Application Number: CN201610885299 |