Method and apparatus for cache access mode selection

• Main Authors: SHANNON STEPHEN ROBERT, VENKUMAHANTI SURESH KUMAR
• Format: Patent
• Language: Chinese; English
• Published: 22.02.2017
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention relates to a particular method. The method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access. 本发明涉及种特定方法，所述方法包含基于存储在发布队列处的数个指令、执行单元的数个活跃线程，或基于这两者，在第高速缓冲存储器存取模式和第二高速缓冲存储器存取模式之间进行选择。所述方法进步包含执行第高速缓冲存储器存取。当选定所述第高速缓冲存储器存取模式时，执行所述第高速缓冲存储器存取包含执行标记存取，并在执行所述标记存取之后执行数据阵列存取。当选定所述第二高速缓冲存储器存取模式时，执行所述第高速缓冲存储器存取包含与所述数据阵列存取并行地执行所述标记存取。