Storage and calculation array structure and operation method thereof
The invention discloses a storage and calculation array structure and an operation method thereof. The array structure comprises a resistive unit crossing rod array M, first to fourth gate regions S1 to S4, n bit line voltage sources U1n to Unn, m word line voltage sources Um1 to Umm, n bit line gro...
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Main Authors | , , , , |
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Format | Patent |
Language | Chinese English |
Published |
01.02.2017
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Subjects | |
Online Access | Get full text |
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Summary: | The invention discloses a storage and calculation array structure and an operation method thereof. The array structure comprises a resistive unit crossing rod array M, first to fourth gate regions S1 to S4, n bit line voltage sources U1n to Unn, m word line voltage sources Um1 to Umm, n bit line grounding resistors R1n to Rnn and m word line grounding resistors Rm1 to Rmm, wherein the resistive unit crossing rod array is separated from the voltage sources and the grounding resistors through the gate regions; when the storage and calculation array structure is used for calculation, the gate regions are used for realizing the gating on the grounding resistors, the voltage sources and the resistive units participating in the calculation; a material implication (IMP) logic circuit is formed. The conventional IMP logic-based resistive array is expanded, so that the IMP calculation can be performed on the resistive unit in a certain row, and can also be performed on the resistive unit in a certain line; the utiliza |
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Bibliography: | Application Number: CN201610863551 |