Semiconductor substrate

• Main Author: CHAO CHIENANG
• Format: Patent
• Language: Chinese; English
• Published: 07.12.2016
• Subjects: BASIC ELECTRIC ELEMENTS; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGYGENERATION, TRANSMISSION OR DISTRIBUTION; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

A semiconductor substrate is provided in the present invention, including a semiconductor body, a first buffer layer, a first amorphous silicon layer, a second buffer layer, a second amorphous silicon layer and a first protective layer. The semiconductor body has a first surface and a second surface relative to the first surface. The first buffer layer is disposed on the first surface of the semiconductor body. The first amorphous silicon layer doped with a first type dopant is disposed on the first buffer layer. The second buffer layer is disposed on the second surface of the semiconductor body. The second amorphous silicon layer doped with a second type dopant is disposed on the second buffer layer. The protective layer is disposed on the first amorphous silicon layer. 本发明公开种半导体基板，包含半导体本体、第缓冲层、第非晶硅层、第二缓冲层、第二非晶硅层与第保护层。半导体本体具有第表面与相对于第表面的第二表面。第缓冲层设置于半导体本体的第表面上。第非晶硅层掺杂有第型掺质且设置于第缓冲层上。第二缓冲层设置于半导体本体的第二表面上。第二非晶硅层掺杂有第二型掺质且设置于第二缓冲层上。第保护层设置于第非晶硅层上。