Method and circuit for reducing collector-emitter voltage overshoot in an insulated gate bipolar transistor

A circuit for reducing collector-emitter voltage (VCE) overshoot in an insulated gate bipolar transistor (IGBT) is provided. The circuit includes circuitry operable to generate a pulse which has a rising edge synchronized to the moment when collector or emitter current of the IGBT begins to fall dur...

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Bibliographic Details
Main Authors MA KWOK WAI, CHEUNG SUI PUNG
Format Patent
LanguageChinese
English
Published 23.11.2016
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Summary:A circuit for reducing collector-emitter voltage (VCE) overshoot in an insulated gate bipolar transistor (IGBT) is provided. The circuit includes circuitry operable to generate a pulse which has a rising edge synchronized to the moment when collector or emitter current of the IGBT begins to fall during turn-off of the IGBT and a width which is a fraction of a duration of the VCE overshoot. The circuitry is further operable to combine the pulse with a control signal applied to a gate of the IGBT so as to momentarily raise the gate voltage of the IGBT during turn-off of the IGBT to above a threshold voltage of the IGBT for the duration of the pulse. A corresponding method of reducing VCE overshoot in an IGBT also is provided. 提供了种用于减小绝缘栅双极型晶体管(IGBT)中的集电极-发射极电压(V)过冲的电路。电路包括可操作以生成具有与IGBT的集电极或发射极电流在IGBT的关闭期间开始下降的时刻同步的上升沿以及作为V过冲的持续时间的部分的宽度的脉冲的电路装置。电路装置还可操作以将脉冲与向IGBT的栅极施加的控制信号组合以针对所述脉冲的持续时间在所述开关周期的所述第二阶段中将所述IGBT的所述栅极电压暂时升高至所述IGBT的门限电压以上。提供了种减小IGBT中的V过冲的对应方法。
Bibliography:Application Number: CN20161317627