Instruction dispatching method for executing packet padding idle rhythms by means of skip target basic blocks

Disclosed is an instruction dispatching method for executing packet padding idle rhythms by means of skip target basic blocks. The instruction dispatching method comprises the following steps that 1, a code flow graph is searched for a target basic block pair related to the operation for executing p...

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Bibliographic Details
Main Authors QIU YAQIONG, HU YONGHUA, LI GUOHUI, HUANG WENTI
Format Patent
LanguageChinese
English
Published 12.10.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Disclosed is an instruction dispatching method for executing packet padding idle rhythms by means of skip target basic blocks. The instruction dispatching method comprises the following steps that 1, a code flow graph is searched for a target basic block pair related to the operation for executing packet padding idle rhythms through spanning basic block selection; 2, predecessor execution packet determination is performed on instruction execution packets inside the skip target basic blocks, other instructions relied by various instructions inside the execution packets are determined, the execution packets where the relied instructions are located and the positions of the execution packets are determined, and the rhythms corresponding to the earliest executable time of the execution packets are determined according to the dependency among the instructions; 3, according to the positional relation between the idle rhythms inside the basic blocks and the rhythms corresponding to the earliest executable time of th
Bibliography:Application Number: CN20161370406