Time sharing storage circuit structure used in OTN packet switching interface chip

• Main Authors: JIANG LIN, YANG WANGMING, YANG BOWEN, MENG LILIN, LI SAI
• Format: Patent
• Language: Chinese; English
• Published: 07.09.2016
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses a circuit structure capable of asynchronously processing data at a high speed, and the circuit structure supports data transmission from a low speed interface to a high speed interface. The circuit structure can be applied to transmission in an OTN. A data packet needs to be transmitted to the high speed interface to perform exchange when clock signals having various frequencies existing in data unit modules are processed, and packet switching between an OTN chip and an external chip is performed, and lots of asynchronous FIFO circuits are required; data packet output is polled, FIFO addresses and polling addresses can generate a huge address selection network, and then the circuit operation speed is decreased; the circuit structure separates the lots of FIFO circuits and recombines the FIFO circuits; and one control circuit and four dual port RAMs are combined to a new circuit structure which can process data cross clock domains. 本发明公开了种高速异步处理数据的电路结构，支持低速接口向高速接口数据传输。这种结构适用于OTN中的传输，因为在