Multi-level cell designs for high density low power gshe-stt mram

• Main Authors: WU WENQING, YUEN KENDRICK HOY LEONG, ARABI KARIM
• Format: Patent
• Language: Chinese; English
• Published: 31.08.2016
• Subjects: ELECTRICITY; INFORMATION STORAGE; PHYSICS; STATIC STORES

Systems and methods are directed to multi-level cell (MLC) comprising: two or more programmable elements coupled to a common access transistor, wherein each one of the two or more programmable elements has a corresponding unique set of two or more switching resistances and two or more switching currents characteristics, such that combinations of the two or more programmable elements configured in the respective two or more switching resistance correspond to multi-bit binary states controllable by passing switching currents through the common access transistor. Each one of the two or more programmable elements includes one or more hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magneto-resistive random access memory (MRAM) cell, with two or more hybrid GSHE-STT MRAM cells coupled in parallel. 本发明的系统和方法是针对多电平单元MLC，其包括：耦合到共同存取晶体管的两个或更多个可编程元件，其中所述两个或更多个可编程元件中的每者具有组对应的两个或更多个唯切换电阻和两个或更多个切换电流特性，以使得在相应两个或更多个切换电阻中配置的所述两个或更多个可编程元件的组合对应于多位二进制状态，所述多位二进制状态可通过使切换电流通过所述共同存取晶体管来控制。所述两个或更多个可编程元件中的每者包含或多个混合巨自旋霍