Multi-threshold asymmetric configuration memory used for single-particle reinforcement FPGA (Field Programmable Gate Array)

• Main Authors: WANG WENFENG, CHEN LEI, NI JIE, LI XUEWU, ZHANG YANLONG, ZHANG ZHILONG, SUN HUABO, ZHAO YUANFU
• Format: Patent
• Language: Chinese; English
• Published: 06.07.2016
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

The invention discloses a multi-threshold asymmetric configuration memory used for a single-particle reinforcement FPGA (Field Programmable Gate Array). The configuration memory uses a plurality of MOS (Metal Oxide Semiconductor) tubes which have unequal threshold values and different breadth length ratios, and PMOS (P-channel Metal Oxide Semiconductor) tubes with a pull-up function, and the circuit, the domain and the technological parameters of the configuration memory are asymmetric to realize a purpose that the initial states of the configuration memory are all zero after the FPGA is powered on and before the FPGA is reset. The configuration memory consists of eight PMOS tubes and eight NMOS (N-channel Metal Oxide Semiconductor) tubes, wherein two of the eight PMOS tubes have high threshold values and the small breadth length ratio, and two groups independently adopt two PMOS tubes to form two circuits with the pull-up function; and two of another eight NMOS tubes have high threshold values and the small