Dual-CPU delay control circuit

• Main Authors: ZHANG HANGQI, CAI YANPING, CAI YUNWEN, XIAO ZHENLONG, CHEN RUTAO
• Format: Patent
• Language: Chinese; English
• Published: 15.06.2016
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

The invention discloses a dual-CPU delay control circuit, comprising a monostable delay circuit, a master CPU control signal input end, a first diode, a second diode and a slave CPU control signal output circuit, wherein the monostable delay circuit is provided with an external trigger signal input end, and the output end of the monostable delay circuit is connected with the positive pole of the second diode; the master CPU control signal input end is connected with the positive pole of the first diode; the negative poles of the first and second diodes are both connected with the input end of the slave CPU control signal output circuit, an external trigger signal is delayed by the monostable delay circuit, thus the slave CPU starts at first to make the corresponding functions start at first, then after the master CPU starts, the master CPU takes over the power supply control of the slave CPU, and thereby the control on the overall functionality is achieved. 种双CPU延迟控制电路，包括单稳态延迟电路、主CPU控制信号输入端、第二极管、第二二极管和从CPU控制信