NUMA memory management fault tolerance method based on TLB-MISS
The invention provides an NUMA memory management fault tolerance method based on TLB-MISS. The method comprises the steps that a processor is powered on to enter a processing entrance of a microcode; the on-site condition of memories is judged, and a difference value between a lowest address in phys...
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Main Authors | , , , , |
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Format | Patent |
Language | English |
Published |
13.01.2016
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Subjects | |
Online Access | Get full text |
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Summary: | The invention provides an NUMA memory management fault tolerance method based on TLB-MISS. The method comprises the steps that a processor is powered on to enter a processing entrance of a microcode; the on-site condition of memories is judged, and a difference value between a lowest address in physical addresses of the on-site memory and zero is calculated; the difference value is saved; all TLB entries in the processor are cleared; a virtual address entrance of a processor core is carried out to start to operate a processor core code; if processor TLM-MISS abnormity is triggered in the processor core code operating process, the processor enters a TLB-MISS abnormity processing entrance to carry out a TLB-MISS abnormity processing program; the corresponding relationship between a virtual address and the physical addresses is calculated in the TLB-MISS abnormity processing program according to the difference value, and a correct TLB entry is filled according to the corresponding relationship; the processor exits the TLB-MISS abnormity processing program, returns to the code triggering the TLB-MISS abnormity and carries out the code triggering the TLB-MISS abnormity again. |
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Bibliography: | Application Number: CN20151831797 |