Liner and barrier applications for subtractive metal integration

Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a c...

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Main Authors KNISLEY, THOMAS JOSEPH, WU, HUI-JUNG, SHANKAR, NAGRAJ, SHEN, MEIHUA, SHARMA, PRITHU, HOANG, JOHN
Format Patent
LanguageEnglish
Published 06.01.2016
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.
Bibliography:Application Number: CN201510374339