NAND flash memory error control code structure and error code control method thereof

• Main Authors: TAN XUEQING, JIANG XIAOBO
• Format: Patent
• Language: English
• Published: 23.09.2015
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The present invention discloses an NAND flash memory error control code structure, comprising an ECC coder having a bit rate of 0.4 to 0.9, an ECC decoder having a bit rate of 0.4 to 0.9, and an NAND flash memory controller. The present invention further discloses an error code control method of the NAND flash memory error control code structure, comprising the following steps: 1. acquiring to NAND flash memories under different processes, acquiring a relationship between a raw bit error ratio (RBRR) and erasable times of the flash memory; 2. calculating an acceptable RBER when UBER is less than 10 to 15; 3. calculating the erasable times of the flash memory under different RRERs according to the previously acquired relationship between the erasable times and the RBER of the flash memory under different processes; 4. calculating a non-error bit integral information capacity of the flash memory; and 5. selecting a bit rate of the ECC. According to the present invention, the non-error bit integral information capacity can be ensured to the maximum and the long-term stability of the NAND flash memory can be ensured.