Semiconductor technological formula loading method and system

• Main Author: PAN YUHAN
• Format: Patent
• Language: English
• Published: 01.07.2015
• Subjects: BASIC ELECTRIC ELEMENTS; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS; CONTROL OR REGULATING SYSTEMS IN GENERAL; CONTROLLING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS; PHYSICS; REGULATING; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

The invention discloses a semiconductor technological formula loading method and system. The method comprises setting a Recipe editing page of deep silicon etching equipment as an initial loading page; reading machine type data from semiconductor technology tasks and detecting the machine type according to reading results; loading the initial loading page to perform formula editing when the machine type is the deep silicon etching equipment; when the machine type is IC etching equipment, creating a father Recipe of the same name for all sub Recipes in the semiconductor technology tasks dynamically respectively to generate a current technology configured RecipeCon.xml file according to the generated current technology, and loading the Recipe editing page of the IC etching equipment to perform formula editing. The Recipe editing pages of the two different types of the machines of the deep silicon etching equipment and the IC etching equipment are compatible in one window in the mode of RecipeCon.xml file organizing of Recipe editing pages, and accordingly, developer maintenance operations are reduced, and the system correction risk is reduced.