High-speed FPGA realization method applied to MQ arithmetic encoder based on deep running water

• Main Authors: TAO HONGJIANG, JIN LONGXU, ZHANG RANFENG, HAO XIANPENG, ZHANG KE
• Format: Patent
• Language: English
• Published: 03.06.2015
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PICTORIAL COMMUNICATION, e.g. TELEVISION

The invention relates to a high-speed FPGA (Field Programmable Gate Array) realization method applied to an MQ arithmetic encoder based on deep running water and belongs to the field of computers and digital image processing. In order to improve the execution speed of an MQ coding algorithm, on the basis of an original four-level assembly line structure, through more reasonably distributing the workload and expanding an assembly line, a novel fast MQ arithmetic coding realization mode based on six levels of assembly lines is provided; through reasonably distributing the workload, the necessary serial workload in the same level of assembly line is reduced; through increasing the number of levels of the assembly line, the maximum transformation workload in each level of assembly line is reduced; through analyzing a control signal of a related link between CX table update and arithmetic coding interval A update, a novel realization mode of three-level decomposition through an advanced prediction access technology and a multi-index value analysis and selection technology, namely the first three levels of assembly lines are obtained; the addition speed and the multi-way selection speed are improved through a novel register allocation way, so that the overall execution speed of the MQ coder is improved.