LDMOS transistor structure and preparation method thereof

• Main Author: CAO GUOHAO
• Format: Patent
• Language: English
• Published: 27.05.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention provides an LDMOS transistor structure and a preparation method thereof. The LDMOS transistor structure comprises a semiconductor substrate, a first high-voltage well region, a second high-voltage well region, a third high-voltage well region, a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region, a source region, a drain region, a body extraction region, a gate region and contact holes at least, wherein the contact holes are formed in the source region, the drain region, the body extraction region and the gate region respectively; the contact holes formed in the gate region are specifically distributed in one side of a gate polysilicon layer above the second shallow trench isolation region. According to the invention, the contact holes are re-distributed in the gate polysilicon layer above the second shallow trench isolation region, so that the electric field distribution on the gate region is more uniform, the region within the range of an intersection of the source region and the gate region is subjected to no negative impact; the area of the LDMOS device occupied in the entire chip is reduced from the design, so as to reduce the sizes of the chips of customers finally.