ELECTRONIC CIRCUIT HAVING SERIAL LATCH SCAN CHAINS

Disclosed is an electronic circuit 10 with latch scan chains 12, the circuit has a built-in test structure 14, generation means 16 that simultaneously generates scan-in data for each of the scan chains, and interception means 18 that intercepts test lines 20 of the scan chains. The test lines having...

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Bibliographic Details
Main Authors CEDRIC LICHTENAU, ANDREAS KOENIG, TILMAN GLOEKLER, JENS KUENZER
Format Patent
LanguageEnglish
Published 29.04.2015
Subjects
CONTROL OR REGULATING SYSTEMS IN GENERAL
CONTROLLING
FUNCTIONAL ELEMENTS OF SUCH SYSTEMS
MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS
PHYSICS
REGULATING
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Summary:Disclosed is an electronic circuit 10 with latch scan chains 12, the circuit has a built-in test structure 14, generation means 16 that simultaneously generates scan-in data for each of the scan chains, and interception means 18 that intercepts test lines 20 of the scan chains. The test lines having scan-in lines 22 and/or control lines 24. The interception means are responsive to the generation means in order to feed the generated scan-in data into each of the scan chains for initializing the electronic circuit. The test structure may input the scan-in data in parallel into the scan chains. The interception means may intercept the scan-in lines and the control lines, and the generation means may fetch pre-configured data from a memory for feeding into the scan-in lines. Also disclosed is a method of initialising the electronic circuit.
Bibliography:Application Number: CN201410559612