Field effect transistor with composite passivation-layer structure

• Main Authors: LIU DONG, PAN PEILIN, BAI ZHIYUAN, DU JIANGFENG, CHEN NANTING, YU QI
• Format: Patent
• Language: English
• Published: 11.02.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention discloses a field effect transistor with a composite passivation-layer structure. The field effect transistor sequentially and mainly comprises a substrate, a gallium-nitride buffer layer, a gallium-nitride channel layer, an aluminum-gallium-nitrogen barrier layer, a source electrode and a drain electrode from bottom to top, wherein the source electrode and the drain electrode are formed on the barrier layer, the drain electrode, the source electrode and the barrier layer are formed into ohmic contact, and a passivation layer covers the surface of a device. The passivation layer between a grid electrode and the drain electrode is formed by transversely compounding an insulating material (high-K dielectric) with a higher dielectric constant with an insulating material (low-K dielectric) with a lower dielectric constant. Because surrounding electric-field distribution can be changed by a boundary which is formed by high-K and low-K dielectric layers, an electric-field peak value is introduced into a device channel, so that the electron gas of the channel is sufficiently exhausted, so as to enhance the voltage-withstanding capability of the device.