Sealing ring structure of chip

• Main Authors: XU LIANG, SONG CHUN, CHEN WENLEI, ZHANG QIANG, ZHAI XIAOYONG
• Format: Patent
• Language: English
• Published: 11.02.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention provides a sealing ring structure of a chip. The sealing ring structure comprises an inner sealing ring and an outer sealing ring, wherein the inner sealing ring is arranged surrounding an integrated circuit area and is provided with an aluminum weld pad; the outer sealing ring is arranged surrounding the inner sealing ring; the inner sealing ring comprises one or more first sub sealing rings, one or more second sub sealing rings and first dielectric isolation rings, wherein the one or more first sub sealing rings are coupled to the aluminum weld pad and are arranged close to the outer sealing ring, and each first sub sealing ring comprises a group of sealing strips, which are arranged along the circumferential direction and are independent of one another, and dielectric isolation strips which are used for isolating adjacent sealing strips; the one or more second sub sealing rings are arranged close to the integrated circuit area; the first dielectric isolation rings are arranged between the first sub sealing rings and the second sub sealing rings, so as to isolate the second sub sealing rings from the aluminum weld pad and the first sub sealing rings. According to the sealing ring structure of the chip, the second sub sealing rings are isolated from the aluminum weld pad and the first sub sealing rings by using the first dielectric isolation rings, and the first sub sealing rings are isolated into the mutually-independent sealing strips by using the dielectric isolation strips, so that the defect that the integrated circuit area is failed due to short circuit is avoided.