Managed instruction cache prefetching

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: indentifying common...

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Main Authors HYUSEINOVA MIREM, STAVROU KYRIAKOS A, LUPON MARC, MADRILES CARLOS, TOURNAVITIS GEORGIOS, MARTINEZ VICENTE ALEJANDRO, XEKALAKIS POLYCHRONIS, GOMEZ REQUENA CRISPIN, MARTINEZ RAUL, GIBERT CODINA ENRIC, ORTEGA DANIEL, KOTSELIDIS CHRISTOS E, MAGKLIS GRIGORIOS, MARCUELLO PEDRO, PAVLOU DEMOS, LATORRE FERNANDO, GONZALEZ ANTONIO, LOPEZ PEDRO, CODINA JOSEP M
Format Patent
LanguageChinese
English
Published 17.12.2014
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: indentifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.
Bibliography:Application Number: CN201180076122