Stacked comparator topology for multi-level signaling
A system and method for detecting signal levels in a multi-level signaling receiver. In one embodiment, a plurality of comparators, each including a differential pair, such as a differential pair of field-effect transistors (FETs) are assembled in a stacked configuration so that in some states curre...
Saved in:
Main Author | |
---|---|
Format | Patent |
Language | Chinese English |
Published |
22.10.2014
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | A system and method for detecting signal levels in a multi-level signaling receiver. In one embodiment, a plurality of comparators, each including a differential pair, such as a differential pair of field-effect transistors (FETs) are assembled in a stacked configuration so that in some states current flows through FETs of the plurality of differential pairs in series, resulting in a reduction in power consumption. |
---|---|
Bibliography: | Application Number: CN201410161902 |