Two-phase mutually non-overlap clock circuit and method thereof

Disclosed in the invention is a two-phase mutually non-overlap clock circuit comprising an input buffer unit, a first NOT gate, a first time delay unit, a second time delay unit, a first AND gate, a second AND gate, a first output buffer unit, and a second output buffer unit. The input terminal of t...

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Bibliographic Details
Main Authors DENG RUOHAN, HUANG YI
Format Patent
LanguageChinese
English
Published 22.10.2014
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:Disclosed in the invention is a two-phase mutually non-overlap clock circuit comprising an input buffer unit, a first NOT gate, a first time delay unit, a second time delay unit, a first AND gate, a second AND gate, a first output buffer unit, and a second output buffer unit. The input terminal of the first NOT gate is connected with the output terminal of the input buffer unit; the input terminal of the first time delay unit is connected with the output terminal of the first NOT gate; the input terminal of the second time delay unit is connected with the output terminal of the first time delay unit; the input terminal of the first AND gate is respectively connected with the output terminal of the input buffer unit and the output terminal of the first time delay unit; the input terminal of the second AND gate is respectively connected with the output terminal of the first NOT gate and the output terminal of the second time delay unit; the input terminal of the first output buffer unit is connected with the ou
Bibliography:Application Number: CN20141291168