Internal plasma grid for semiconductor fabrication

• Main Authors: VAHEDI, VAHID, PATERSON, ALEX, SINGH, HARMEET, LILL, THORSTEN, MARSH, RICHARD A, SRIRAMAN, SARAVANAPRIYAN, WU, YING
• Format: Patent
• Language: Chinese; English
• Published: 15.10.2014
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid may have slots of a particular aspect ratio which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The lower sub-chamber plasma has a lower electron density, lower effective electron temperature, and higher negative ion:positive ion ratio as compared to the upper sub-chamber plasma. The disclosed embodiments may result in an etching process having good center to edge uniformity, selectivity, profile angle, and Iso/Dense loading.