用于能量效率和节能的方法、装置和系统，包括使用寄存器次级不间断电源的改进的处理器核深断电退出等待时间

• Format: Patent
• Language: Chinese
• Published: 17.10.2017
• Subjects: CALCULATING; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; PHYSICS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

本发明的实施例涉及改进从计算机设备处理器核深断电中的离开等待时间。通过向驻留在处理器的临界状态寄存器内的常开保持器电路提供次级不间断电源，可在深断电模式期间维持处理器状态数据。当这些寄存器接收到指示处理器功率状态将要从活动处理器功率状态减少为零处理器功率状态的控制信号时，它们将临界状态数据从临界状态寄存器的锁存器写到被提供有不间断电源的保持器电路。然后，当寄存器接收到指示处理器的处理器功率状态将要增加回活动处理器功率状态的控制信号时，存储于保持器电路内的临界状态数据被写回临界状态寄存器的锁存器。 Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be i