Synchronously resettable scanning structure D trigger resisting single event upset and single event transient

• Main Authors: GUO YANG, LIANG BIN, LIU ZONGLIN, CHI YAQING, HU CHUNMEI, CHEN JIANJUN, WANG YUNFENG, LI ZHENTAO, SUN YONGJIE, CHEN SHUMING
• Format: Patent
• Language: Chinese; English
• Published: 28.05.2014
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

The invention discloses a synchronously resettable scanning structure D trigger resisting single event upset and single event transient, so as to solve the problem of poor ability to resist single event upset and single event transient of the synchronously resettable scanning structure D trigger. According to the invention, the synchronously resettable scanning structure D trigger is composed of a buffer circuit, a scanning control buffer circuit, a synchronous reset buffer circuit, a clock circuit, a master latch, a slave latch and an inverter circuit; the master latch and the slave latch are redundant reinforcement latches; the master latch and the slave latch are connected in series, and are connected with the clock circuit; the master latch is connected with the buffer circuit, the scanning control buffer circuit and the synchronous reset buffer circuit; and the slave latch is connected with the inverter circuit. Mutually redundant C2MOS circuits in the master latch and the slave latch are separated, whic