Method for manufacturing shallow groove isolation

• Main Author: ZENG SHAOHAI
• Format: Patent
• Language: Chinese; English
• Published: 16.04.2014
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention relates to a method for manufacturing a shallow groove isolation. The method comprises the steps that a substrate is provided, wherein a pad oxidation layer and an etching barrier layer are sequentially formed on the substrate; the etching barrier layer, the pad oxidation layer and the substrate are etched to form a shallow groove located in the substrate; an isolating layer is formed on the surface of the shallow groove; a polysilicon layer fully filled into the shallow groove is formed on the surface of the isolating layer; germanium is poured into the formed stacked structure ion and annealing treatment is performed. Therefore, on the basis that the method is compatible to an existing technology, the method for manufacturing the shallow groove isolation also has the advantages that channel stress is enhanced by filling the strain isolating materials into the shallow groove, the performance of CMOS components is improved, the investment for improving the environment needed in the technology pr